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MF1P2131DA4/02 Fiches technique(PDF) 5 Page - NXP Semiconductors |
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MF1P2131DA4/02 Fiches technique(HTML) 5 Page - NXP Semiconductors |
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5 / 33 page ![]() NXP Semiconductors MF1P(H)x1y1 MIFARE Plus EV1 MF1P(H)x1y1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product short data sheet Rev. 3.2 — 6 December 2018 COMPANY PUBLIC 366932 5 / 33 6 Block diagram 001aah389 RF INTERFACE UART ISO/IEC 14443A AES CRYPTO CO-PROCESSOR CPU/LOGIC UNIT CRC EEPROM RAM ROM TRUE RANDOM NUMBER GENERATOR CRYPTO1 SECURITY SENSORS POWER ON RESET VOLTAGE REGULATOR CLOCK INPUT FILTER RESET GENERATOR Figure 1. Block diagram 7 Pinning information 7.1 Pinning 001aam200 top view LA LB Figure 2. Pin configuration of the contactless module (MOA4 and MOB6) 7.2 Pin description Table 3. Pin description (MOA4 and MOB6) Symbol Pin Description LA LA antenna coil connection LA LB LB antenna coil connection LB |
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