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SH7041A Fiches technique(PDF) 833 Page - Renesas Technology Corp |
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SH7041A Fiches technique(HTML) 833 Page - Renesas Technology Corp |
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833 / 923 page ![]() 795 Tp CK A21–A0 Tr Tc1 Tcw1 Tc2 t AD t AD t RP t RASD1 t ASR t CASD1 t RAH t RASD2 t CASD2 t CAC t RAC t AA t RDS t RDH t CASD2 t RWD2 t WDH t DH t DS t WDD t DACKD1 t DACKD1 t RSD1 t WSD1 t WSD2 t RSD2 t CASD1 t RWD1 Row address Column address RAS CASxx RDWR D31–D0 CASxx RDWR D31–D0 DACKn RD WRxx Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and CAS. (During read) (During read) (During read) (During read) (During write) (During write) (During write) (During write) Figure 26.12 DRAM Cycle (Normal Mode, 1 Wait, TPC = 0, RCD = 0) |
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