SH7041A datasheet(824/923 Pages) RENESAS

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26.3.2

Control Signal Timing

Table 26.5

Control Signal Timing (Conditions: V

CC = 3.0

*1 to 3.6V, AV

CC = 3.0

*1 to 3.6V,

CC = VCC ± 10%, AVref = 3.0

*1 to AV

CC, VSS = AVSS = 0V, Ta = –20 to +75°C)

Item

Symbol

Min

Max

Unit

Figure

RES rise/fall

RESr, t RESf

—

200

26.4

RES pulse width

RESW

—

cyc

MRES pulse width

MRESW

—

cyc

NMI rise/fall

NMIr, t NMIf

—

200

26.5

RES setup time*

RESS

100

—

26.4

MRES setup time*

MRESS

100

—

26.5

NMI setup time (during edge detection)

NMIS

100

—

IRQ7–IRQ0 setup time (edge detection)*

IRQES

100

—

IRQ7–IRQ0 setup time (level detection)*

IRQLS

100

—

NMI hold time

NMIH

—

26.5

IRQ7–IRQ0 hold time

IRQEH

—

IRQOUT output delay time

IRQOD

—

26.6

Bus request setup time

BRQS

—

26.7

Bus acknowledge delay time 1

BACKD1

—35ns

Bus acknowledge delay time 2

BACKD2

—35ns

Bus three state delay time

BZD

—35ns

Notes: *1 SH7042/43 ZTAT (excluding A mask) are 3.2V.

*2 The

RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are asynchronous inputs, but

when the setup times shown here are provided, the signals are considered to have

produced changes at clock rise (for

RES, MRES, BREQ) or clock fall (for NMI and

IRQ7–IRQ0). If the setup times are not provided, recognition is delayed until the next

clock rise or fall.

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