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SH7041A Fiches technique(PDF) 800 Page - Renesas Technology Corp |
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SH7041A Fiches technique(HTML) 800 Page - Renesas Technology Corp |
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800 / 923 page ![]() 762 Tp Tr Tc1 Tc2 t AD t AD t ASR t RP t RASD1 t RAH t CASD1 t CAC t AA t RAC t RDS t RASD2 t CASD2 t RDH t RWD1 t CASD2 t CASD1 t RWD2 t WDH t DH t DS t WDD t DACKD1 t DACKD1 t RSD1 t RSD2 t WSD1 t WSD2 CK A21–A0 RAS CASxx RDWR D31– D0 D31–D0 CASxx RDWR DACKn RD WRxx Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and CAS. (During read) (During read) (During read) (During read) (During write) (During write) (During write) (During write) Row address Column address Figure 25.11 DRAM Cycle (Normal Mode, No Waits, TPC = 0, RCD = 0) |
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