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SH7041A Fiches technique(PDF) 590 Page - Renesas Technology Corp

No de pièce SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Fiches technique(HTML) 590 Page - Renesas Technology Corp

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Figure 15.7 shows an example of operation in the group-scan mode when AN0–AN2 are selected.
ADDRB
ADDRA
Channel 3
Channel 2
Channel 1
Channel 0
ADST
ADF
ADDRC
ADDRD
Sam-
pling
1
Sam-
pling
4
Sam-
pling
2
Conver-
sion
standby
Conversion standby
Sam-
pling
5
Sam-
pling
3
Sam-
pling
6
A/D
conver-
sion 1
A/D
conver-
sion 4
A/D
conver-
sion 2
A/D
conver-
sion 5
A/D
conver-
sion 3
Conversion
standby
Conversion standby
Conversion standby
Conver-
sion
standby
Conver-
sion
standby
Cleared to 0 by software
Set to 1 by software
Conversion result 1
Conversion result 4
Conversion result 5
Conversion result 2
Conversion result 3
Conver-
sion
stopped
Figure 15.7 A/D Converter Operation Example (Group-Scan Mode)
15.4.5
Buffer Operation
When conversion ends on the relevant channel, the conversion result is stored in the ADDR, and
simultaneously, the previously stored result is transferred to another ADDR. Buffer operation can
be selected from the following:
• AN0 → ADDRA → ADDRB (Two-stage, one-group operation)
• AN0 → ADDRA → ADDRC, AN1 → ADDRB → ADDRD (Two-stage, two-group
operation)
• AN0 → ADDRA → ADDRB → ADDRC → ADDRD (Four-stage, one-group operation)



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