SH7041A datasheet(574/923 Pages) RENESAS

No de pièce	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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Fabricant	RENESAS [Renesas Technology Corp]

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574 / 923 page

536

14.5.7

Constraints on DMAC/DTC Use

• When using an external clock source for the synchronization clock, update the TDR with the

DMAC or the DTC, and then after five system clocks or more elapse, input a transmit clock. If

a transmit clock is input in the first four system clocks after the TDR is written, an error may

occur (figure 14.25).

• Before reading the receive data register (RDR) with the DMAC/DTC, select the receive-data-

full interrupt of the SCI as a start-up source.

SCK

TDRE

Note: During external clock operation, an error may occur if t is 4

φ or less.

Figure 14.25 Example of Clock Synchronous Transmission with DMAC

14.5.8

Cautions for Clock Synchronous External Clock Mode

• Set TE = RE = 1 only when the external clock SCK is 1.

• Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed

from 0 to 1.

• When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the

RxD D7 bit SCK input, but it cannot be copied to RDR.

14.5.9

Caution for Clock Synchronous Internal Clock Mode

When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7

bit SCK output, but it cannot be copied to RDR.

SH7041A Fiches technique(PDF) 574 Page - Renesas Technology Corp