SH7041A datasheet(567/923 Pages) RENESAS

No de pièce	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

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Error handling

End

Clear ORER bit of SSR to 0

Overrun error processing

Figure 14.21 Sample Flowchart for Serial Receiving (2)

Figure 14.22 shows an example of the SCI receive operation.

Bit 7

Bit 0

Bit 7

Bit 0

Bit 1

Bit 6

Synchroni-

zation clock

Serial

data

Transfer direction

Bit 7

Read data with RxI

interrupt processing

routine and clear

RDRF bit to 0

1 frame

RxI request

ERI interrupt

request generated

by overrun error

RDRF

ORER

Figure 14.22 Example of SCI Receive Operation

In receiving, the SCI operates as follows:

1.The SCI synchronizes with serial clock input or output and initializes internally.

2.Receive data is shifted into the RSR in order from the LSB to the MSB.After receiving the

data, the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the

RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in the RDR. If

the check does not pass (receive error), the SCI operates as indicated in table 14.11 and no

further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set

SH7041A Fiches technique(PDF) 567 Page - Renesas Technology Corp