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SH7041A Fiches technique(PDF) 385 Page - Renesas Technology Corp |
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SH7041A Fiches technique(HTML) 385 Page - Renesas Technology Corp |
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385 / 923 page ![]() 347 input clock is used as the TGR0B register input capture source, and a pulse width of four times the 2-phase encoder pulse is detected. The channel 1 TGR1A and TGR1B registers are set for the input capture function, the channel 0 TGR0A and TGR0C register compare-match is used as an input capture source, and all of the control period increment and decrement values are stored. TCLKA TCLKB Edge detection circuit TCNT1 TCNT0 TGR1A (speed period capture) TGR0A (speed control period) TGR0C (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) TGR1B (position period capture) Channel 0 Channel 1 + – + – Figure 12.34 Phase Count Mode Application Example |
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