7 / 11 page  MDT10P55A This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2006/1 Ver. 1.3 Instruction Code Mnemonic Operands Function Operating Status 010001 1rrrrrrr STWR R Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) ↔R(4~7)] →t None 011001 trrrrrrr INCR R, t Increment register R + 1→t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t or (R+/W+1→t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t Z 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t None 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ⊕ W→t Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ⊕ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR R, t Rotate right register R(n) →R(n-1), C→R(7), R(0)→C C 010101 trrrrrrr RLR R, t Rotate left register R(n)→r(n+1), C→R(0), R(7)→C C 010000 1xxxxxxx CLRW Clear working register 0→W Z 010001 0rrrrrrr CLRR R Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1000nn nnnnnnnn LCALL n Long CALL subroutine n→PC, PC+1→Stack None 1010nn nnnnnnnn LJUMP n Long JUMP to address n→PC None 110000 nnnnnnnn CALL n Call subroutine n→PC, PC+1→Stack None 110001 iiiiiiii RTWI i Return, place immediate to W Stack→PC,i→W None 11001n nnnnnnnn JUMP n JUMP to address n→PC None |
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