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PDP83TG720SWCSTQ1 Fiches technique(PDF) 5 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Fiches technique(HTML) 5 Page - Texas Instruments |
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5 / 199 page ![]() PIN STATE(1) DESCRIPTION NAME NO. XO 4 O Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI. LED/GPIO INTERFACE LED_0 / GPIO_0 35 S, PD, IO LED_0: Link Status LED_1 / GPIO_1 6 S, PD, IO LED_1: Link Status and BLINK for TX/RX Activity CLKOUT / GPIO_2 16 IO Clock Output: 25-MHz reference clock(buffered replication of XI) by default. Can be configured to output different clock sources. MEDIUM DEPENDENT INTERFACE TRD_M 13 IO Differential Transmit and Receive: Bidirectional differential signaling configured for 1000BASE-T1 operation, IEEE 802.3bp compliant. TRD_P 12 POWER AND GROUND CONNECTIONS VDDA3P3 11 SUPPLY Core Supply: 3.3 V. Refer to power supply recommendations for decoupling network. VDDIO 22, 34 SUPPLY IO Supply: 1.8 V, 2.5 V, or 3.3 V. Refer to power supply recommendations for decoupling network. VDD1P0 9, 21 SUPPLY Core Supply: 1.0 V. Refer to power supply recommendations for decoupling network. VSLEEP 7 SUPPLY Sleep Supply: 3.3 V. Refer to power supply recommendations for decoupling network. This pin shall be tied to VDDA3P3 if sleep functionality is not used. GROUND DAP GROUND Ground DO NOT CONNECT DNC 17, 18, 19, 20 DNC DNC: Do Not Connect (floating) (1) Type: I = Input O = Output IO = Input/Output OD = Open Drain PD = Internal Pulldown PU = Internal Pullup S = Strap: Configuration pin (all configuration pins have weak internal pullups or pulldowns) www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 |
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