PIC24H datasheet(17/290 Pages) MICROCHIP

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Preliminary

DS70175D-page 17

PIC24H

2.0

CPU

The PIC24H CPU module has a 16-bit (data) modified

Harvard architecture with an enhanced instruction set

and addressing modes. The CPU has a 24-bit instruction

word with a variable length opcode field. The Program

Counter (PC) is 23 bits wide and addresses up to 4M x

24 bits of user program memory space. The actual

amount of program memory implemented varies by

device. A single-cycle instruction prefetch mechanism is

used

help

maintain

throughput

and

provides

predictable execution. All instructions execute in a single

cycle, with the exception of instructions that change the

program flow, the double word move (MOV.D) instruction

and the table instructions. Overhead-free, single-cycle

program loop constructs are supported using the

REPEAT

instruction, which is interruptible at any point.

The PIC24H devices have sixteen, 16-bit working

registers in the programmer’s model. Each of the working

registers can serve as a data, address or address offset

software Stack Pointer (SP) for interrupts and calls.

The PIC24H instruction set includes many addressing

modes and is designed for optimum C compiler

efficiency. For most instructions, the PIC24H is capable

of executing a data (or program data) memory read, a

working register (data) read, a data memory write and

a program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing A + B = C operations to be

executed in a single cycle.

A block diagram of the CPU is shown in Figure 2-1,

and the programmer’s model for the PIC24H is shown

in Figure 2-2.

2.1

Data Addressing Overview

The data space can be linearly addressed as 32K words

or 64 Kbytes using an Address Generation Unit (AGU).

The upper 32 Kbytes of the data space memory map can

optionally be mapped into program space at any 16K

program word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM,

which is primarily used for DMA data transfers, but may

be used as general purpose RAM.

2.2

Special MCU Features

The PIC24H features a 17-bit by 17-bit, single-cycle

multiplier. The multiplier can perform signed, unsigned

and mixed-sign multiplication. Using a 17-bit by 17-bit

multiplier for 16-bit by 16-bit multiplication makes

mixed-sign multiplication possible.

The PIC24H supports 16/16 and 32/16 integer divide

operations.

All

divide

instructions

are

iterative

operations. They must be executed within a REPEAT

loop, resulting in a total execution time of 19 instruction

cycles. The divide operation can be interrupted during

any of those 19 cycles without loss of data.

A multi-bit data shifter is used to perform up to a 16-bit,

left or right shift in a single cycle.

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

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