STM32MP151C datasheet(42/253 Pages) STMICROELECTRONICS

42 / 253 page

Functional overview

STM32MP151C/F

42/253

DS12501 Rev 3

3.31

Cryptographic and hash processors (CRYP1, CRYP2 and

HASH1, HASH2)

The devices embed two cryptographic processors that support the advanced cryptographic

algorithms usually required to ensure confidentiality, authentication, data integrity and non-

repudiation when exchanging messages with a peer:

•

Encryption/decryption

–

DES/TDES (data encryption standard/triple data encryption standard): ECB

(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,

128- or 192-bit key

–

AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter

mode) chaining algorithms, 128, 192 or 256-bit key

•

Universal HASH

–

SHA-1, SHA224 and SHA256 (secure HASH algorithms)

–MD5

–HMAC

The cryptographic accelerator supports DMA request generation.

CRYP1 and HASH1 can be defined (in ETZPC) as accessible by secure software only.

3.32

Boot and security and OTP control (BSEC)

The BSEC (boot and security and OTP control) is intended to control an OTP (one time

programmable) fuse box, used for embedded non-volatile storage for device configuration

and security parameters. Some part of BSEC should be configured as accessible by secure

software only.

3.33

Timers and watchdogs

The devices include two advanced-control timers, ten general-purpose timers, two basic

timers, five low-power timers, three watchdogs, a SysTick timer in Cortex-M4 and 4 system

timers in Cortex-A7.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control, general-purpose, basic and low-

power timers.

STM32MP151C Fiches technique(PDF) 42 Page - STMicroelectronics