LPC802 datasheet(36/83 Pages) NXP

36 / 83 page

LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

36 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

9.24 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is

configured to support up to four breakpoints and two watch points.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC802 is

in reset. The JTAG boundary scan pins are selected by hardware when the part is in

boundary scan mode. See Table 4.

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250

s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

LPC802 Fiches technique(PDF) 36 Page - NXP Semiconductors