ADAU1977WBCPZ-R7 datasheet(43/68 Pages) AD

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Data Sheet

ADAU1977

Rev. C | Page 43 of 68

SERIAL PORT CONTROL REGISTER2

Address: 0x06, Reset: 0x00, Name: SAI_CTRL1

Table 32. Bit Descriptions for SAI_CTRL1

Bits

Bit Name

Settings

Description

Reset

Access

SDATA_SEL

SDATAOUTx Pin Selection in TDM4 or Greater Modes.

0x0

SDATAOUT1 used for output

SDATAOUT2 used for output

[6:5]

SLOT_WIDTH

Number of BCLKs per Slot in TDM Mode.

0x0

32 BCLKs per TDM slot

24 BCLKs per TDM slot

16 BCLKs per TDM slot

Reserved

DATA_WIDTH

Output Data Bit Width.

0x0

24-bit data

16-bit data

LR_MODE

Sets LRCLK Mode.

0x0

50% duty cycle clock

Pulse—LRCLK is a single BCLK cycle wide pulse

SAI_MSB

Sets Data to be Input/Output either MSB or LSB First.

0x0

MSB first data

LSB first data

BCLKRATE

Sets the Number of Bit Clock Cycles per Data Channel Generated When in

Master Mode.

0x0

32 BCLKs/channel

16 BCLKs/channel

SAI_MS

Sets the Serial Port into Master or Slave Mode.

0x0

LRCLK/BCLK Slave

LRCLK/BCLK Master

ADAU1977WBCPZ-R7 Fiches technique(PDF) 43 Page - Analog Devices

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