MB9BF412RPMC-G-JNE2 datasheet(103/112 Pages) CYPRESS

103 / 112 page

Document Number: 002-05615 Rev. *D

Page

103 of 112

MB9B410R Series

Operation example of return from low power consumption mode (by internal resource reset*)

Internal

resource

reset

tRCNT

Internal reset

CPU

Operation

Start

Reset active

Release

*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.

Notes:

− The return factor is different in each Low-Power consumption modes.

See "CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes" in "FM3 Family PERIPHERAL

MANUAL."

− When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power

consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL

MANUAL".

− The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset Timing" in "4. AC

Characteristics" in "12 Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage

detection reset.

− When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL

clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait

time.

− The internal resource reset means the watchdog reset and the CSV reset.

MB9BF412RPMC-G-JNE2 Fiches technique(PDF) 103 Page - Cypress Semiconductor