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WM8775EDS/R Fiches technique(PDF) 20 Page - Wolfson Microelectronics plc

No de pièce WM8775EDS/R
Description  24 BIT 96 KHZ ADC WITH 4 CHANNEL I/P MULTIPLEXER
PDF  36 Pages
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Fabricant  WOLFSON [Wolfson Microelectronics plc]
Site Internet  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8775EDS/R Fiches technique(HTML) 20 Page - Wolfson Microelectronics plc

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WM8775
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PP Rev 1.8, June 2004
20
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
In left/right/ I
2S modes:
ADCLRC Polarity (normal)
0 : normal ADCLRC polarity
1: inverted ADCLRC polarity
R11(0Bh)
0001011
Interface Control
2
ADCLRP
0
In DSP mode:
0 : Early DSP mode
1: Late DSP mode
By default, ADCLRC is sampled on the rising edge of BCLK and should ideally change on the falling
edge. Data sources that change ADCLRC on the rising edge of BCLK can be supported by setting
the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in
Figures 12, 13, 14, and 15.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11(0Bh)
0001011
Interface Control
3
ADCBCP
0
BCLK Polarity (DSP modes)
0 : normal BCLK polarity
1: inverted BCLK polarity
The WL[1:0] bits are used to control the input word length.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11(0Bh)
0001011
Interface Control
5:4
ADCWL
[1:0]
10
Word Length
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
Note:
1.
If 32-bit mode is selected in right justified mode, the WM8775 defaults to 24 bits.
2.
In 24 bit I
2S mode, any width of 24 bits or less is supported provided that ADCLRC is high for a
minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
ADC MASTER MODE
Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC
and BCLK are outputs and are generated by the WM8775. In Slave mode ADCLRC and BCLK are
inputs to WM8775.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12(0Ch)
0001100
Interface Control
8
ADCMS
0
Audio Interface Master/Slave Mode
select:
0 : Slave Mode
1: Master Mode
MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8775 generates ADCLRC and BCLK. These clocks are derived from the
master clock. The ratio of MCLK to ADCLRC is set by ADCRATE.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12(0Ch)
0001100
ADCLRC Frequency
Select
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC
ratio select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs



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