STM32L471RG datasheet(30/218 Pages) STMICROELECTRONICS

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Functional overview

STM32L471xx

30/218

DocID027226 Rev 1

3.10

Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run

and sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 6. STM32L471xx peripherals interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

Timers synchronization or chaining

ADCx

DACx

DFSDM

Conversion triggers

DMA

Memory to memory transfer trigger

COMPx

Comparator output blanking

COMPx

TIM1, 8

TIM2, 3

Timer input channel, trigger, break from

analog signals comparison

LPTIMERx

Low-power timer triggered by analog

signals comparison

(1)

ADCx

TIM1, 8

Timer triggered by analog watchdog

RTC

TIM16

Timer input channel from RTC events

LPTIMERx

Low-power timer triggered by RTC alarms

or tampers

(1)

All clocks sources (internal

and external)

TIM2

TIM15, 16, 17

Clock source used as input channel for

RC measurement and trimming

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

DFSDM (analog

watchdog, short circuit

detection)

TIM1,8

TIM15,16,17

Timer break

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