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STM32L471RG Fiches technique(PDF) 53 Page - STMicroelectronics

No de pièce STM32L471RG
Description  Batch acquisition mode
PDF  218 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L471RG Fiches technique(HTML) 53 Page - STMicroelectronics

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STM32L471xx
Functional overview
55
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbyte of data
•
8-,16- bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.34
Quad SPI memory interface (QUADSPI)
The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
•
Indirect mode: all the operations are performed using the QUADSPI registers
•
Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external flash is memory mapped and is seen by the
system as if it were an internal memory



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