ST10F296 datasheet(106/346 Pages) STMICROELECTRONICS

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Capture/compare (CAPCOM) units

ST10F296E

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Capture/compare (CAPCOM) units

The ST10F296E has two 16 channel CAPCOM units as shown in Figure 21: CAPCOM unit

block diagram. These support generation and control of timing sequences on up to 32

channels with a maximum resolution of 125 ns at 64 MHz CPU clock. The CAPCOM units

are typically used to handle high speed I/O tasks such as pulse and waveform generation,

PMW, digital to analog (D/A) conversion, software timing, or time recording relative to

external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases

for the capture/compare register array (see Figure 22 and Figure 23).

The input clock for the timers is programmable to several prescaled values of the internal

system clock, or it may be derived from an overflow/underflow of Timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows precise

adjustments for application-specific requirements. In addition, external count inputs for

CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers

relative to external events.

Each of the two capture/compare register arrays contain 16 dual purpose capture/compare

registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7

or T8, respectively), and programmed for capture or compare functions. Each of the 32

registers has one associated port pin which serves as an input pin for triggering the capture

function, or as an output pin to indicate the occurrence of a compare event. Figure 21 shows

the basic structure of the two CAPCOM units.

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