ST10F296 datasheet(103/346 Pages) STMICROELECTRONICS

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ST10F296E

Interrupt system

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9.1

XPeripheral interrupt

The limited number of XBus interrupt lines of the present ST10 architecture, imposes some

constraints on the implementation of the new functionality. In particular, the additional

XPeripherals SSC1, ASC1, I2C, PWM1, and RTC need some resources to implement

interrupt and PEC transfer capabilities. For this reason, a sophisticated but very flexible

multiplexed structure for the interrupt management is proposed (see Figure 20). It shows the

basic structure replicated for each of the four XInterrupt available vectors (XP0INT, XP1INT,

XP2INT, and XP3INT).

It is based on a set of 16-bit registers XIRxSEL (x = 0, 1, 2, 3), divided into two portions

each:

●

Byte high, XIRxSEL[15:8]: Interrupt enable bits

●

Byte low, XIRxSEL[7:0]: Interrupt flag bits

When different sources submit an interrupt request, the enable bits (byte high of the

XIRxSEL register) define a mask which controls which sources are associated with the

unique available vector. If more than one source is enabled to issue the request, the service

routine has to identify the real event to be serviced. This can be done by checking the flag

bits (byte low of the XIRxSEL register). Note that the flag bits can also provide information

about events which are not currently serviced by the interrupt controller (since they are

masked through the enable bits). This allows effective software management in the absence

of the possibility to serve the related interrupt request. A periodic polling of the flag bits may

be implemented inside the user application.

Note:

The XIRxSEL registers are mapped into the XMiscellaneous area. Therefore, they can be

accessed only if the XMISCEN and XPEN bits are set in the XPERCON and SYSCON

registers respectively.

Figure 20.

XInterrupt basic structure

XIRxSEL[7:0] (x = 0, 1, 2, 3)

XIRxSEL[15:8] (x = 0, 1, 2, 3)

XPxIC.XPxIR (x = 0, 1, 2, 3)

IT source 7

IT source 6

IT source 5

IT source 4

IT source 3

IT source 2

IT source 1

IT source 0

Enable[7:0]

Flag[7:0]

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