PC87338 datasheet(23/221 Pages) NSC

23 / 221 page

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ASTRB

Group 11

Address Strobe. This active-low signal is used in EPP mode as an

address strobe.

ASTRB is multiplexed with SLIN and STEP. See Table 72 for more

information.

BADDR0

BADDR1

Group 1

SIO Base Address Straps 0 and 1. These bits must be externally

strapped to determine which one of four base address options for

the INDEX and DATA registers will be used by the system after

reset. See Table 8.

If BADDR1 = 0 and BADDR0 = 1 during reset, the chip “wakes up”

without a base address and the Plug and Play protocol should be

applied. For more details see Section 2.

These pins are internally grounded by a 30 K

Ω pull-down resistor.

To strap these pins high, pull them up to Vcc with a 10 KΩ resistor.

BADDR0 is multiplexed with RTS1, and BADDR1 is multiplexed with

SOUT1 (and BOUT1 in PC87338 only).

BOUT1

BOUT2

(71)

(63)

(69)

(61)

Group 7

SCC Baud Output signals 1 and 2. These multi-function pins

provide the associated serial channel Baud Rate generator output

signal for SCC1 or SCC2, if test mode is selected in the Power and

Test Configuration Register (PTR) and the DLAB bit (LCR7) is set.

BOUT1 is multiplexed with SOUT1 and BADDR1. BOUT2 is

multiplexed with SOUT2, IRTX and CFG0 (in PC87338 only).

BOUT1 is multiplexed with DTR1. BOUT2 is multiplexed with DTR2

and A12 (in PC97338 only).

BUSY

Group 2

Busy. This parallel port signal is set high by the external printer

when it cannot accept another character.

This pin is internally grounded by a nominal 25 K

Ω pull-down

resistor.

BUSY is multiplexed with MTR1 and WAIT. (See Table 72 for more

information).

CFG0

Group 9

Configuration. This CMOS input signal is externally strapped to

select one of two default configurations in which the Chip powers

up (see Table 6).

This pin is internally grounded by a 30 K

Ω pull-down resistor. To

strap this pin high, pull it up to VCC with a 10 KΩ resistor.

CFG0 is multiplexed with SOUT2 and IRTX.

CS0

CS1

Group 8

Programmable Chip Select signals 0 and 1. CS1,0 are

programmable chip select and/or latch enable and/or output enable

signals that can be used as game port, I/O expander, etc.

The decoded address and the assertion conditions are configured

via the Chip configuration registers, indexed by 0Ah-0Dh, 10h-11h,

03h and 4Dh.

CS1,0 are push-pull output signals.

CS0 is multiplexed with DRATE1, MSEN1, SIRQI2 and DACK3.

CS1 is multiplexed with ZWS.

Symbol

PQFP

TQFP

I/O and

Group #

Function

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