PC87338 datasheet(16/221 Pages) NSC

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TABLE 50 Effect of GDC Bits on FORMAT TRACK and WRITE DATA Commands .................................... 104

TABLE 51 Skip Control Effect on READ DATA Command ........................................................................... 107

TABLE 52 Result Phase Termination Values with No Error .......................................................................... 108

TABLE 53 SK Effect on READ DELETED DATA Command ........................................................................ 108

TABLE 54 Maximum RECALIBRATE Step Pulses for Values of R255 and ETR .......................................... 111

TABLE 55 The Effect of Scan Commands on the ST2 Register ................................................................... 113

TABLE 56 Interrupt Causes Reported by SENSE INTERRUPT ................................................................... 114

TABLE 57 Defining Bytes to Read or Write Using SET TRACK .................................................................... 116

TABLE 58 Constant Multipliers for Delay After Processing Factor and Delay Ranges ................................ 117

TABLE 59 Constant Multipliers for Delay Before Processing Factor and Delay Ranges ............................. 117

TABLE 60 STEP Time Interval Calculation .................................................................................................. 117

TABLE 61 VERIFY Command Termination Conditions ................................................................................ . 119

TABLE 62 Parallel Port Reset States ........................................................................................................... 124

TABLE 63 Standard Parallel Port Registers

................................................................................................ 124

TABLE 64 SPP Data Register Read and Write Modes ................................................................................. 125

TABLE 65 EPP Revision Selection ................................................................................................................ 127

TABLE 66 Parallel Port Registers in EPP Modes .......................................................................................... 128

TABLE 67 ECP Modes Encoding .................................................................................................................. 133

TABLE 68 Parallel Port Registers in ECP Modes .......................................................................................... 134

TABLE 69 ECP Mode DMA Selection .......................................................................................................... 140

TABLE 70 ECP Mode Interrupt Selection ...................................................................................................... 140

TABLE 71 ECP Modes ................................................................................................................................. 141

TABLE 72 Parallel Port Pin Out ..................................................................................................................... 144

TABLE 73 Register Bank Summary ............................................................................................................. 153

TABLE 74 Bank 0 Serial Controller Base Registers þ ................................................................................... 153

TABLE 75 Non-Extended Mode Interrupt Priorities ....................................................................................... 155

TABLE 76 TX_FIFO Level Selection ............................................................................................................ 157

TABLE 77 RX_FIFO Level Selection ............................................................................................................. 157

TABLE 78 Word Length Select Encoding ...................................................................................................... 158

TABLE 79 Bit Settings for Parity Control ....................................................................................................... 158

TABLE 80 Bank Selection Encoding ............................................................................................................. 159

TABLE 81 The Module Operation Modes ...................................................................................................... 160

TABLE 82 Bank 1 Register Set ..................................................................................................................... 163

TABLE 83 Bank 2 Register Set ..................................................................................................................... 164

TABLE 84 Baud Generator Divisor Settings .................................................................................................. 165

TABLE 85 Bank 3 Register Set ..................................................................................................................... 168

TABLE 86 Bank 4 Register Set ..................................................................................................................... 169

TABLE 87 Bank 5 Register ............................................................................................................................ 170

TABLE 88 Bank 6 Register Set ..................................................................................................................... 173

TABLE 89 MIR Pulse Width Settings ............................................................................................................. 174

TABLE 90 FIR Preamble Length ................................................................................................................... 174

TABLE 91 MIR Beginning Flags .................................................................................................................... 175

TABLE 92 Bank 7 Register Set ..................................................................................................................... 175

TABLE 93 CEIR, Low Speed Demodulator (RXHSC = 0) (Frequency Ranges in kHz)þ .............................. 176

TABLE 94 Consumer IR High Speed Demodulator Frequency Ranges in kHz (RXHSC = 1) ..................... 177

TABLE 95 Sharp-IR Demodulator Frequency Ranges in kHz ....................................................................... 177

TABLE 96 CEIR Carrier Frequency Encoding ............................................................................................... 178

TABLE 97 Infrared Receiver Input Selection ................................................................................................. 182

TABLE 98 DMA Support in Legacy Mode .................................................................................................... 190

TABLE 99 DMA Support in Plug and Play Mode ........................................................................................... 190

TABLE 100 Interrupt Support in Legacy Mode for IRQ3, 4, 6, 7, 9 10 and 11 ............................................. 191

PC87338 Fiches technique(PDF) 16 Page - National Semiconductor (TI)

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