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STMPE321 Fiches technique(PDF) 15 Page - STMicroelectronics |
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STMPE321 Fiches technique(HTML) 15 Page - STMicroelectronics |
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15 / 40 page ![]() STMPE321 System and identification registers Doc ID 15791 Rev 3 15/40 ID_VER Revision number Address: 0x02 Type: R Reset: 0x03 Description: 8-bit revision number SYS_CFG_1 System configuration 1 Address: 0x03 Type: R/W Reset: 0x00 Description: The reset control register enables the reset of the device 76 543 2 1 0 RESERVED SLEEP WARM_RESET SOFT_RESET HIBERNATE [7:4] RESERVED [3] SLEEP: Write ‘1’ to enable sleep mode. Hardware resets this bit to ‘0’ after it successfully enters sleep mode. [2] WARM_RESET: Write ‘1’ to initiate a warm reset. Register content remains, state machine reset. [1] SOFT_RESET: Write ‘1’ to initiate a soft reset. All registers content and state machines reset. [0] HIBERNATE: Force the device into hibernation mode. Write ‘1’ to enter hibernate mode. Hardware resets this bit to ‘0’ after it successfully enters hibernate mode. |
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