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DS17885 Fiches technique(PDF) 27 Page - Dallas Semiconductor |
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DS17885 Fiches technique(HTML) 27 Page - Dallas Semiconductor |
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27 / 38 page ![]() DS17885/DS17887 27 of 38 RTC AC TIMING CHARACTERISTICS Over the operating range (3V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Cycle Time tCYC 360 DC ns Pulse-Width, RD / WR Low PWRWL 200 ns Pulse-Width, RD / WR High PWRWH 150 ns Input Rise and Fall tR, tF 30 ns Chip-Select Setup Time Before WR or RD tCS 20 ns Chip-Select Hold Time tCH 0ns Read Data Hold Time tDHR 10 90 ns Write Data Hold Time tDHW 0ns Muxed Address Valid Time to ALE Fall tASL 40 ns Muxed Address Hold Time to ALE Fall tAHL 10 ns RD or WR High Setup to ALE Rise tASD 30 ns Pulse-Width ALE High PWASH 40 ns ALE Low Setup to RD or WR Fall tASED 30 ns Output Data-Delay Time from RD tDDR 20 200 ns 6 Data Setup Time tDSW 70 ns IRQ Release from RD tIRD 2 ms AC TEST CONDITIONS Output Load: 50pF Input Pulse Levels: 0V to 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns |
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