| Moteur de recherche de fiches techniques de composants électroniques |
|
SST49LF080A Fiches technique(PDF) 1 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
SST49LF080A Fiches technique(HTML) 1 Page - Microchip Technology |
|
1 / 50 page ![]() ©2014 Silicon Storage Technology, Inc. DS20005086B 11/14 Data Sheet www.microchip.com Features • LPC Interface Flash – SST49LF080A: 1024K x8 (8 Mbit) • Conforms to Intel LPC Interface Specification 1.0 • Flexible Erase Capability – Uniform 4 KByte Sectors – Uniform 64 KByte overlay blocks – 64 KByte Top Boot Block protection – Chip-Erase for PP Mode Only • Single 3.0-3.6V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Read Current: 6 mA (typical) – Standby Current: 10 µA (typical) • Fast Sector-Erase/Byte-Program Operation – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 16 seconds (typical) – Single-pulse Program or Erase – Internal timing generation • Two Operational Modes – Low Pin Count (LPC) Interface mode for in-system operation – Parallel Programming (PP) Mode for fast production pro- gramming • LPC Interface Mode – 5-signal communication interface supporting byte Read and Write – 33 MHz clock frequency operation – WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block – Standard SDP Command Set – Data# Polling and Toggle Bit for End-of-Write detection – 5 GPI pins for system design flexibility – 4 ID pins for multi-chip selection • Parallel Programming (PP) Mode – 11-pin multiplexed address and 8-pin data I/O interface – Supports fast programming In-System on programmer equipment • CMOS and PCI I/O Compatibility • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) • All non-Pb (lead-free) devices are RoHS compliant 8 Mbit LPC Flash SST49LF080A The SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment. The SST49LF080A flash memory device is manu- factured with proprietary, high-performance SuperFlash® Technology. The split- gate cell design and thick-oxide tunneling injector attain better reliability and man- ufacturability compared with alternate approaches |
Numéro de pièce similaire - SST49LF080A |
|
Description similaire - SST49LF080A |
|
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |