SST49LF080A datasheet(8/50 Pages) MICROCHIP

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DS20005086B

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8 Mbit LPC Flash

SST49LF080A

Data Sheet

LPC Mode

Device Operation

The LPC mode uses a 5-signal communication interface, a 4-bit address/data bus, LAD[3:0], and a

control line, LFRAME#, to control operations of the SST49LF080A. Cycle type operations such as

Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specification, Revision

1.0. JEDEC Standard SDP (Software Data Protection) Program and Erase commands sequences are

incorporated into the standard LPC memory cycles. See Figures 7 through 12 for command

sequences.

LPC signals are transmitted via the 4-bit Address/Data bus (LAD[3:0]), and follow a particular

sequence, depending on whether they are Read or Write operations. LPC memory Read and Write

cycle is defined in Tables 5 and 6.

Both LPC Read and Write operations start in a similar way as shown in Figures 5 and 6. The host

(which is the term used here to describe the device driving the memory) asserts LFRAME# for two or

more clocks and drives a start value on the LAD[3:0] bus.

At the beginning of an operation, the host may hold the LFRAME# active for several clock cycles, and

even change the Start value. The LAD[3:0] bus is latched every rising edge of the clock. On the cycle

in which LFRAME# goes inactive, the last latched value is taken as the Start value. CE# must be

asserted one cycle before the start cycle to select the SST49LF080A for Read and Write operations.

Once the SST49LF080A identifies the operation as valid (a start value of all zeros), it next expects a

nibble that indicates whether this is a memory Read or Write cycle. Once this is received, the device is

now ready for the Address cycles. The LPC protocol supports a 32-bit address phase. The

SST49LF080A encodes ID and register space access in the address field. See Table 3 for address bits

definition.

For Write operation the Data cycle will follow the Address cycle, and for Read operation TAR and

SYNC cycles occur between the Address and Data cycles. At the end of every operation, the control of

the bus must be returned to the host by a 2-clock TAR cycle.

Table 3: Address bits definition

A31:A251

1. The top 32MByte address range FFFF FFFFH to FE00 0000H and the bottom 128 KByte memory access address

000F FFFFH to 000E 0000H are decoded.

A24:A23

A22

A21:A20

A19:A0

1111 111b or 0000 000b

ID[3:2]2

2. See Table 7 for multiple device selection configuration

1 = Memory Access

0 = Register access

ID[1:0]2

Device Memory address

T3.1 25026

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