USB3450 datasheet(14/39 Pages) MICROCHIP

14 / 39 page

USB3450

DS00002105A-page 14

 2005 - 2016 Microchip Technology Inc.

5.0

DETAILED FUNCTIONAL OVERVIEW

FIGURE 2-1: on page 5 shows the functional block diagram of the USB3450. Each of the functions is described in detail

below.

5.1

8bit Bi-Directional Data Bus Operation

The USB3450 supports an 8-bit bi-directional parallel interface.

• CLKOUT runs at 60MHz

• The 8-bit data bus (DATA[7:0]) is used for transmit when TXVALID = 1

• The 8-bit data bus (DATA[7:0]) is used for receive when TXVALID = 0

Figure 5-1 shows the relationship between CLKOUT and the transmit data transfer signals in FS mode. TXREADY is

only asserted for one CLKOUT per byte time to signal the Link that the data on the DATA lines has been read by the

PHY. The Link may hold the data on the DATA lines for the duration of the byte time. Transitions of TXVALID must meet

the defined setup and hold times relative to CLKOUT.

Figure 5-2 shows the relationship between CLKOUT and the receive data control signals in FS mode. RXACTIVE

“frames” a packet, transitioning only at the beginning and end of a packet. However transitions of RXVALID may take

place any time 8 bits of data are available. Figure 5-2 also shows how RXVALID is only asserted for one CLKOUT cycle

per byte time even though the data may be presented for the full byte time. The XCVRSELECT signal determines

whether the HS or FS timing relationship is applied to the data and control signals.

FIGURE 5-1:

FS CLK RELATIONSHIP TO TRANSMIT DATA AND CONTROL SIGNALS

FIGURE 5-2:

FS CLK RELATIONSHIP TO RECEIVE DATA AND CONTROL SIGNALS

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