| Moteur de recherche de fiches techniques de composants électroniques |
|
PC87373 Fiches technique(PDF) 40 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87373 Fiches technique(HTML) 40 Page - National Semiconductor (TI) |
|
40 / 174 page ![]() 3.0 Device Architecture and Configuration (Continued) 40 www.national.com Revision 1.1 3.3 MODULE CONTROL Module control is performed primarily through the Activation bit (bit 0 of index 30h) of each logical device. 3.3.1 Module Enable/Disable Module control is performed primarily through the Activation bit (bit 0 of index 30h) of each logical device. The operation of each module can be controlled by the host through the LPC bus. Module enable/disable by the host through the LPC bus is controlled by the following bits: q Activation bit (bit 0) in index 30h of the Standard configuration registers (see Section 3.2.3 on page 36) q Fast Disable bit in SIOCF6 register; for the FDC, Parallel Port and Serial Port (1 and 2) modules only (see Section 3.7.6 on page 47) q Global Enable bit (GLOBEN) in SIOCF1 register (see Section 3.7.2 on page 44) A module is enabled only if all of these bits are set to their “enable” value. When a VDD3-powered module (FDC, Parallel Port, Serial Ports, KBC, MIDI Port and Game Port, FSCM) is disabled, the following takes place: q The host system resources of the logical device (IRQ, DMA and runtime address range) are unassigned. q Access to the standard- and device-specific Logical Device configuration registers through the LPC bus remains en- abled. q Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is not generated). q The module’s internal clock is disabled (the module is not functional) to lower the power consumption. When a VSB3-powered module (GPIO and SWC) is disabled, the following takes place: q The host system resources of the logical device (IRQ and runtime address range) are unassigned. q Access to the standard and device specific Logical Device configuration registers through the LPC bus remains en- abled. q Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is not generated). q The module is functional. |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |