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CS9211 Fiches technique(PDF) 59 Page - National Semiconductor (TI) |
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CS9211 Fiches technique(HTML) 59 Page - National Semiconductor (TI) |
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59 / 62 page ![]() Revision 2.1 59 www.national.com Electrical Specifications (Continued) Figure 5-10. Active Matrix TFT Color Panel Output Timing Table 5-14. Active Matrix TFT Color Panel Timing Characteristics Symbol Parameter Min Max Units Comments (Note 1) TP1 SHFCLK period 30 ns TP2 SHFCLK high time 5 ns TP3 SHFCLK low time 5 ns TP4 SHFCLK rise time 3 ns TP5 SHFCLK fall time 3 ns TP6 Valid data to SHFCLK falling edge (Data setup time) 3ns TP7 UD[11:0] and LD[11:0] hold time (Dataholdtime) 5ns TP8 HSYNC width 500 ns TP9 LDE active to SHFCLK inactive (LDE setup time) 3ns TP10 SHFCLK inactive to LDE inactive (LDE Hold time) 7ns 1. All AC tests, unless otherwise specified, are at: VDD = 3.14 to 3.46 (3.3V nominal), TC =0 oCto 85oC, and C L =50 pF. SHFCLK TP6 TP1 TP3 TP9 TP10 TP8 TP4 TP5 TP2 LDE TP7 HSYNC UD[11:0] , LD[11:0] |
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