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CS9211 Fiches technique(PDF) 58 Page - National Semiconductor (TI) |
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CS9211 Fiches technique(HTML) 58 Page - National Semiconductor (TI) |
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58 / 62 page ![]() www.national.com 58 Revision 2.1 Electrical Specifications (Continued) 5.5.5 Panel Timings Figure 5-8. DSTN Color Panel Output Timing; LP and SHFCLK Relationship Figure 5-9. DSTN Color Panel Output Timing; FLM and LP Relationship Table 5-13. DSTN Color Panel Timing Characteristics Symbol Parameter Min Max Units Comments (Note 1) TP1 SHFCLK period 50 --- ns TP2 SHFCLK high time 15 --- ns TP3 SHFCLK low time 15 --- ns TP4 SHFCLK rise time - 4 ns TP5 SHFCLK fall time 4 ns TP6 Valid data to SHFCLK falling edge (data setup time) 10 ns TP7 SHFCLK falling edge to valid data (dataholdtime) 10 ns TP8 LP pulse width 150 --- ns TP9 FLM setup time 120 --- ns TP10 FLM holdtime(validFLM time after falling edge of LP) 300 -- ns 1. All AC tests, unless otherwise specified, are at: VDD = 3.14 to 3.46 (3.3V nominal), TC =0 oCto 85oC, and C L =50 pF. LP SHFCLK UD[11:0], TP6 TP5 TP4 TP2 TP1 TP3 LD[11:0] TP7 FLM LP TP9 TP10 TP7 |
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