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CS9211 Fiches technique(PDF) 54 Page - National Semiconductor (TI) |
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CS9211 Fiches technique(HTML) 54 Page - National Semiconductor (TI) |
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54 / 62 page ![]() www.national.com 54 Revision 2.1 Electrical Specifications (Continued) 5.5.3 Flat Panel Timing Figure 5-4. Flat Panel Interface Signals Table 5-9. Flat Panel Interface Timing (50 pF Output Load) Symbol Parameter DSTN Mode TFT Mode Units Comments (Note 1) Min Max Min Max tP SHFCLK period 50 --- 30 --- ns tPT SHFCLK rise/fall transition time 4 3 ns tPHP SHFCLK high pulse width 15 --- 5 --- ns tPLP SHFCLK low pulse width 15 --- 5 --- ns tPOS Panel output setup to falling SHF- CLK (Data setup time to the Panel) 10 --- 3 --- ns tPOH Panel output hold from falling SHFCLK (Data hold time to the panel) 10 --- 7 --- ns 1. All AC tests, unless otherwise specified, are at: VDD = 3.14 to 3.46 (3.3V nominal), TC =0 oCto 85oC, and C L =50 pF. SHFCLK tP tPHP tPOH tPOS tPT UD[11:0], LD[11:0] tPLP |
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