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DS3134 Fiches technique(PDF) 196 Page - Dallas Semiconductor

No de pièce DS3134
Description  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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Fabricant  DALLAS [Dallas Semiconductor]
Site Internet  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3134 Fiches technique(HTML) 196 Page - Dallas Semiconductor

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AC CHARACTERISTICS - PCI BUS INTERFACE
(0
°C TO +70°C; VDD = 3.0V TO 3.6V)
Parameter
Symbol
Min
Typ
Max
Units
Notes
PCLK Period
t1
30
40
ns
PCLK Low Time
t2
12
ns
PCLK High Time
t3
12
ns
All PCI Inputs & I/O Set Up Time to the
Rising Edge of PCLK
t4
7
ns
All PCI Inputs & I/O Hold Time from the
Rising Edge of PCLK
t5
0
ns
Delay from the Rising Edge of PCLK to
Data Valid on all PCI Outputs & I/O
t6
2
11
ns
Delay from the Rising Edge of PCLK to
Tri-State on all PCI Outputs & I/O
t7
28
ns
Delay from the Rising Edge of PCLK to
Data Valid from Tri-State on all PCI
Outputs & I/O
t8
2
ns
PCI BUS INTERFACE AC TIMING DIAGRAM Figure 12D
Data Valid
PCLK
PCI Input
& I/O
PCI Output
& I/O
PCI Output &
I/O to Tri-State
PCI Output &
I/O from Tri-State
Data Valid
Tri-State
Tri-State
t4
t5
t6
t7
t8
t1
t2
t3
pci_ac



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