OUT1

IN

GND

EN1

A2

A1

Via

B2

B1

C2

C1

OUT2

EN2

Via

Via

Via

16

LP8900

SNVS542E – MAY 2008 – REVISED JUNE 2016

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Product Folder Links: LP8900

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Copyright © 2008–2016, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

The dynamic performance of the LP8900 is dependant on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP8900.

LP8900 ground pin using as wide and as short of a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, and/or connections through vias must be avoided.

These add parasitic inductances and resistance that results in inferior performance especially during transient

conditions.

11.2 Layout Example

Figure 20. LP8900 Example Layout

11.3 DSBGA Mounting

The DSBGA package requires specific mounting techniques which are detailed in the TI Application Note (AN-

1112) DSBGA Wafer Level Chip Scale Package (SNVA009). Referring to the section Surface Mount Technology

(SMT) Assenbly Considerations, the pad style that must be used with the 6-pin package is a NSMD (non-solder

mask defined) type.

For best results during assembly, alignment ordinals on the PCB may be used to facilitate placement of the

DSBGA device.

11.4 DSBGA Light Sensitivity

Exposing the DSBGA device to direct sunlight may cause mis-operation of the device. Light sources such as

halogen lamps can affect the electrical performance if brought near to the device.

The wavelengths that have the most detrimental effect are reds and infra-reds, which means that the fluorescent

lighting used inside most buildings has little effect on performance.