LSM6DS3H datasheet(38/104 Pages) STMICROELECTRONICS

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Digital interfaces

LSM6DS3H

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DocID028370 Rev 4

Both the read register and write register commands are completed in 16 clock pulses or in

multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling

edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge

of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the

rising edge of CS.

bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)

from the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1-7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods will be added. When the

CTRL3_C (12h) (IF_INC) bit is ‘0’, the address used to read/write data remains the same for

every block. When the CTRL3_C (12h) (IF_INC) bit is ‘1’, the address used to read/write

data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

6.2.1

SPI read

Figure 10. SPI read protocol

The SPI Read command is performed with 16 clock pulses. A multiple byte read command

is performed by adding blocks of 8 clock pulses to the previous one.

bit 0: READ bit. The value is 1.

bit 1-7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

bit 16-...: data DO(...-8). Further data in multiple byte reads.

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