| Moteur de recherche de fiches techniques de composants électroniques |
|
LSM6DS3H Fiches technique(PDF) 37 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
LSM6DS3H Fiches technique(HTML) 37 Page - STMicroelectronics |
|
37 / 104 page ![]() DocID028370 Rev 4 37/104 LSM6DS3H Digital interfaces 104 Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge. 6.2 SPI bus interface The LSM6DS3H SPI is a bus slave. The SPI allows writing and reading the registers of the device. The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO. Figure 9. Read and write protocol CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Table 14. Transfer when master is receiving (reading) one byte of data from slave Master ST SAD + W SUB SR SAD + R NMAK SP Slave SAK SAK SAK DATA Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP Slave SAK SAK SAK DATA DAT A DATA |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |