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M35B32 Fiches technique(PDF) 14 Page - STMicroelectronics

No de pièce M35B32
Description  32 Kbit, 256-byte page, fast program EEPROM memory accessed by SPI bus interface
PDF  44 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M35B32 Fiches technique(HTML) 14 Page - STMicroelectronics

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Memory organization
M35B32
14/44
DocID18391 Rev 4
5
Memory organization
The memory is organized as pages (256 bytes each), with a specific mapping shown in
Figure 5.
The M35B32 decodes addresses from 0000h up to 0FFFh. This makes an address range of
4 Kbytes organized as 16 pages of 256 bytes. The M35B32 can also be seen as two sectors
(the Data sector and the Event sector) which boundary is defined by the BPi status register
bits.
The Data sector (standard EEPROM) is at the top,
The Event sector (offering a fast programming time tFP) is at the bottom. The Event
sector can be also write-protected with pin W.
Both sectors can be erased in a single cycle, with the help of the Sector Erase instruction;
however, each page can be erased using the Page Erase instructions (recommended for
the Data sector).
Figure 5. Memory organization
1. N is defined by the BPi bits (see Section 6.4.3).
Each page can be individually:
programmed (bits are programmed from 1 to 0),
erased (bits are erased from 0 to 1),
written (bits are changed to either 0 or 1).
When the Page Program instruction addresses bytes in the Data sector, the instruction is
executed with the programming time tPP, when the Page Program instruction addresses
bytes in the Event sector, the instruction is executed with the fast programming time tFP.



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