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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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STCOM10 Fiches technique(PDF) 22 Page - STMicroelectronics |
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STCOM10 Fiches technique(HTML) 22 Page - STMicroelectronics |
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22 / 58 page  Description STCOM 22/58 DocID028515 Rev 1 1.7 Reset, control, clock generation (RCC) and system controller (SYS_CTRL) All the clock and reset configuration registers are located in the MISC and SYSCTRL blocks. Figure 3 shows the interaction between these blocks. Figure 3. Reset, clock and system controller interaction The system reset is generated by the RESETn pin (active low). Through the system controller is also possible to assert a system software reset. The software reset to single peripherals can be forced through MISC registers. |
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