AR0330 datasheet(53/77 Pages) ONSEMI

53 / 77 page

AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Slave Mode

The slave mode feature of the AR0330 supports triggering the start of a frame readout

from a VD signal that is supplied from an external ASIC. The slave mode signal allows for

precise control of frame rate and register change updates. The VD signal is input to the

trigger pin. Both the GPI_EN (R0x301A[8]) and the SLAVE_MODE (R0x30CE[4]) bits must

be set to “1” to enable the slave mode.

Figure 36:

Slave Mode Active State and Vertical Blanking

If the slave mode is disabled, the new frame will begin after the extra delay period is

finished.

The slave mode will react to the rising edge of the input VD signal if it is in an active state.

When the VD signal is received, the sensor will begin the frame readout and the slave

mode will remain inactive for the period of one frame time minus 16 clock periods

(TFRAME - (16 / CLK_PIX)). After this period, the slave mode will re-enter the active state

and will respond to the VD signal.

Start of frame N

End of frame N

Start of frame N + 1

Frame Valid

OB Rows (2, 4, or 8 rows)

Embedded Data Row (2 rows)

Active Data Rows

Blank Rows (2 rows)

Extra Vertical Blanking

(frame_length_lines - min_frame_length_lines)

VD Signal

Slave Mode Active State

The period between the

rising edge of the VD signal

and the slave mode ready

state is T

FRAME - 16 clocks.

Extra Delay (clocks)

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