AN413 datasheet(11/45 Pages) STMICROELECTRONICS

11 / 45 page

AN413

ST9 basic system configuration

Doc ID 1875 Rev 2

11/45

Please note that before enabling any A/D conversion, it is mandatory to set the low bit of

Control Logic Register at least 60ms before the first conversion start. This is in order to

correctly bias the analog section of the converter.

The Interrupt Vector Register, IVR, defines the most significant 6 bits of the vector table byte

address. It thus points to the first of two word addresses which correspond to the analog

watchdog and End of conversion interrupt routines.

Example:

F5 FF 32 ld AD_IVR,#ADC_ITEOC_VECT

In this example, an address of 50 (decimal) is loaded into IVR. Hence a subsequent A/D

convertor EOC interrupt will cause a Vector Table access at location 50.

The Interrupt Control Register, ICR, contains the priority level specification, the two source

interrupt flags (Analog Watchdog and EOC) and their individual masking bits.

Example:

F5 FE 20 ld AD_ICR,#00100000b

05 FE 20 or AD_ICR,#00000110b

In this example, the priority level is first set at 0, End of Conversion interrupts are enabled,

and the Analog Watchdog interrupt is masked. The second instruction then sets the priority

to a level of 6.

If the Analog Watchdog is enabled (bit 6 in ICR) it will be necessary to load the threshold

registers for channels 6 and 7. In this case access will be made in the interrupt routine to

The Compare Result Register, CRR, contains 4 flags showing the results of comparison

operations between the current values of data registers 6 and 7, and the upper and lower

threshold registers.

3.6

SCI unit configuration

The list of registers to be initialized when configuring the SCI unit is given in Table 11. The

functions of these registers, and some illustrative examples of their use, are as follows:

The Character Configuration Register, CHCR, is used to define the serial frame format.

Example:

AC E3 ld S_CHCR,#E3h

This example defines a serial frame as follows: 8 data bits, 1 stop bit, even parity, and

address input if the character matches the contents of the Address Register.

The Clock Configuration Register, CLCR, is used to specify the transmitter, receiver, and

Baud Rate clock sources, and the clock divisor ratio. It also enables Auto Echo and

Loopback test modes.

Example:

BC 80 ld s_clcr,#txclk

In this example, the Transmitter and Receiver clocks are provided by the Baud Rate

Generator. Each data bit period will be 16 clock periods (asynchronous mode), and the Auto

Loop and Loopback modes are disabled.

AN413 Fiches technique(PDF) 11 Page - STMicroelectronics

AN413 Fiches technique(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Fiches technique Télécharger

Lien URL