WM8960 datasheet(54/92 Pages) WOLFSON

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WM8960

Production Data

PD, August 2013, Rev 4.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24 (18h)

Additional

Control (2)

LRCM

Selects disable mode for ADCLRC and DACLRC

(Master mode)

0 = ADCLRC disabled when ADC (Left and

Right) disabled; DACLRC disabled when

DAC (Left and Right) disabled.

1 = ADCLRC and DACLRC disabled only when

ADC (Left and Right) and DAC (Left and

Right) are disabled.

Table 35 ADCLRC/DACLRC Enable

COMPANDING

The WM8960 supports A-law and

-law companding on both transmit (ADC) and receive (DAC)

sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate

value to the DACCOMP or ADCCOMP register bits respectively.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R9 (09h)

Audio

Interface (2)

2:1

ADCCOMP

ADC companding

00 = off

01 = reserved

10 = µ-law

11 = A-law

4:3

DACCOMP

DAC companding

00 = off

01 = reserved

10 = µ-law

11 = A-law

WL8

0 = off

1 = device operates in 8-bit mode.

Table 36 Companding Control

Companding involves using a piecewise linear approximation of the following equations (as set out by

ITU-T G.711 standard) for data compression:

-law (where =255 for the U.S. and Japan):

F(x) = ln( 1 +

|x|) / ln( 1 + )

-1 ≤ x ≤ 1

A-law (where A=87.6 for Europe):

F(x) = A|x| / ( 1 + lnA)

 for x ≤ 1/A

F(x) = ( 1 + lnA|x|) / (1 + lnA)

 for 1/A ≤ x ≤ 1

The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted

for

-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s of

data.

Companding converts 13 bits (

-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The

input data range is separated into 8 levels, allowing low amplitude signals better precision than that of

high amplitude signals. This is to exploit the operation of the human auditory system, where louder

sounds do not require as much resolution as quieter sounds. The companded signal is an 8-bit word

containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).

Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to

use 8 BCLK cycles per LRC frame. When using DSP mode B, this allows 8-bit data words to be

output consecutively every 8 BCLK cycles and can be used with 8-bit data words using the A-law and

u-law companding functions.

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