LM3554 datasheet(37/43 Pages) TI1

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1.05V

TX2

TX1/TORCH

Force Torch or

LED Shutdown (VIN Monitor, TX2 or

NTC only)

Internal to

LM3554

LEDI/

NTC

R(T)

0.1 PF

VIN Monitor

BIAS

LM3554

www.ti.com

SNVS549A – JUNE 2009 – REVISED APRIL 2011

Programming bit [3] of the Configuration register with a (1) selects Thermal Comparator mode making the

LEDI/NTC pin a comparator input for flash LED thermal sensing. Figure 28 shows the internal block diagram of

the thermal sensing circuit which is OR’d with both the TX1 and ENVM/TX2 (TX2 mode) to force the LM3554

from Flash to Torch mode. This is intended to prevent LED overheating during flash pulses.

Figure 28. Thermistor Voltage Divider and Sensing Circuit

NTC THERMISTOR PLACEMENT

The termination of the thermistor must be done directly to the cathode of the Flash LED in order to adequately

couple the heat from the LED into the thermistor. Consequentally, the noisy environment generated from the

switching of the LM3554's boost converter can introduce noise from GND into the thermistor sensing input. To

filter out this noise it is necessary to place a 0.1µF or larger ceramic capacitor close to the LEDI/NTC pin. The

filter capacitor's return must also connect with a low-impedance trace, as close as possible to the PGND pin of

the LM3554.

Layout Recommendations

The high frequency and large switching currents of the LM3554 make the choice of layout important. The

following steps should be used as a reference to ensure the device is stable and maintains proper voltage and

current regulation across its intended operating voltage and current range.

1. Place CIN on the top layer (same layer as the LM3554) and as close to the device as possible. The input

capacitor conducts the driver currents during the low-side MOSFET turn-on and turn-off and can see current

spikes over 1A in amplitude. Connecting the input capacitor through short wide traces on both the IN and

GND terminals will reduce the inductive voltage spikes that occur during switching and which can corrupt the

VIN line.

2. Place COUT on the top layer (same layer as the LM3554) and as close as possible to the OUT and GND

terminal. The returns for both CIN and COUT should come together at one point, and as close to the GND pin

as possible. Connecting COUT through short wide traces will reduce the series inductance on the OUT and

GND terminals that can corrupt the VOUT and GND line and cause excessive noise in the device and

surrounding circuitry.

3. Connect the inductor on the top layer close to the SW pin. There should be a low impedance connection

from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the

SW node should be small so as to reduce the capacitive coupling of the high dV/dt present at SW that can

couple into nearby traces.

4. Avoid routing logic traces near the SW node so as to avoid any capacitively coupled voltages from SW onto

any high-impedance logic lines such as TX1/TORCH/GPIO1, ENVM/TX2/GPIO2, HWEN, LEDI/NTC (NTC

mode), SDA, and SCL. A good approach is to insert an inner layer GND plane underneath the SW node and

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