LM3554 datasheet(28/43 Pages) TI1

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R/W

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 7

Bit 6

MSB

LSB

C Slave Address (chip address)

SCL

SDA_IN

SDA_OUT

t 5

t 1

t 4

t 3

LM3554

SNVS549A – JUNE 2009 – REVISED APRIL 2011

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The I2C bus is considered busy after a START condition and free after a STOP condition. During data

transmission the I2C master can generate repeated START conditions. A START and a repeated START

condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock

signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 2 and Figure 17

show the SDA and SCL signal timing for the I2C-Compatible Bus. See the Electrical Characteristics Table for

timing values.

Figure 17. I2C-Compatible Timing

I2C-COMPATIBLE CHIP ADDRESS

The device address for the LM3554 is 1010011 (53). After the START condition, the I2C master sends the 7-bit

address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a

READ. The second byte following the device address selects the register address to which the data will be

written. The third byte contains the data for the selected register.

Figure 18. Device Address

TRANSFERRING DATA

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte

of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is

generated by the master. The master releases SDA (HIGH) during the 9th clock pulse (write mode). The LM3554

pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each

byte has been received.

Table 1. LM3554 Internal Registers

Internal Hex Address

Power On or Reset Value

Torch Brightness

0xA0

0x50

Flash Brightness

0xB0

0x68

Flash Duration

0xC0

0x4F

Flag Register

0xD0

0x40

Configuration Register 1

0xE0

0x42

Configuration Register 2

0xF0

GPIO Register

0x20

0x80

VIN Monitor Register

0x80

0xF0

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