AT45DB011

10

Reset Timing (Inactive Clock Polarity Low Shown)

Command Sequence for Read/Write Operations (Except Status Register Read)

Notes:

1.

“r” designates bits reserved for larger densities.

2.

It is recommended that “r” be a logical “0”.

3.

For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.

CS

SCK

RESET

SO

HIGH IMPEDANCE

HIGH IMPEDANCE

SI

tRST

tREC

tCSS

SI

CMD

8 bits

8 bits

8 bits

MSB

Reserved for

larger densities

Page Address

(PA8-PA0)

Byte/Buffer Address

(BA8-BA0/BFA8-BFA0)

LSB

r r r r

r r X X

X X X X X X X X

X X X X X X X X