AS3675 datasheet(70/81 Pages) AMSCO

70 / 81 page

www.austriamicrosystems.com/AS3675

1v3

69 - 80

AS3675

Datasheet - D e ta i l e d D e s c r i p t i o n

The clock line CLK is never held low by the AS3675 (as the AS3675 does not use clock stretching of the bus).

The AS3675 is compatible to the NXP two wire specification http://www.nxp.com/acrobat_download/literature/9398/

39340011.pdf, Version 2.1, January 2000 for standard and fast mode (no high speed mode) with the following excep-

tion:

Data set-up time for fast mode: tSU;DAT=250ns (instead of 100ns from table 5, p32)

8.11.1 Serial Interface Features

Fast Mode Capability (Maximum Clock Frequency is 400 kHz)

7-bit Addressing Mode

Write Formats

- Single-Byte Write

- Page-Write

Read Formats

- Current-Address Read

- Random-Read

- Sequential-Read

DATA Input Delay and CLK spike filtering by integrated RC components

8.11.2 Device Address Selection

The serial interface address of the AS3675 has the following address:

80h – Write Commands

81h – Read Commands

Figure 35. Complete Serial Data Transfer

Serial Data Transfer Formats

Table 92. Serial Interface Timing

Symbol

Parameter

Condition

Min

Typ

Max

Unit

VIHI/F

High Level Input

Voltage

Pins DATA and CLK

1.38

VBAT

VILI/F

Low Level Input

Voltage

0.0

0.52

VHYSTI/F

Hysteresis

0.1

tRISE

Rise Time

1000

tFALL

Fall Time

300

tCLK_FILTER

Spike Filter on CLK

100

tDATA_FILTER

Spike Filter on DATA

300

Start

Condition

Address R/W

ACK

Data

ACK

Data

ACK

Stop

Condition

DATA

CLK

1-7

AS3675 Fiches technique(PDF) 70 Page - ams AG

AS3675 Fiches technique(HTML) 70 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Fiches technique Télécharger

Lien URL