SPEAR320-2 datasheet(50/73 Pages) STMICROELECTRONICS

No de pièce	SPEAR320-2

Description	Embedded MPU with ARM926 core, optimized for factory automation and consumer applications

PDF	73 Pages

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Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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50 / 73 page

Timing requirements

SPEAr320

50/73

Doc ID 16755 Rev 5

Timing requirements

Note:

Signal transition levels used for timing measurements are 0.2*VDD and 0.8*VDD.

7.1

External interrupt timing characteristics

7.2

Reset timing characteristics

Note:

Warm reset is generated by writing any value to the System controller SYSSTAT register.

7.3

DDR2 timing characteristics

The characterization timing is done considering an output load of 10 pF on all the DDR

pads.

The timing parameters listed are defined by JEDEC for DDR memories. DDR memories

whose parameters are within the ranges defined in Table 29, Table 30 and Table 31 can be

interfaced with SPEAr320.

Read cycle timing apply to DQS and DQ input to SPEAr. Write cycle timings refer to DQS

and DQ output to SPEAr.

Table 27.

PL_GPIO external interrupt input timing

Symbol

Description

Min

Unit

tINT

Minimum width for rising edge interrupt pulse

Table 28.

Cold (power-on) reset

Symbol

Description

Min

Unit

tRP

MRESET pin active low state duration

SPEAR320-2 Fiches technique(PDF) 50 Page - STMicroelectronics