SPEAR320-2 datasheet(56/73 Pages) STMICROELECTRONICS

No de pièce	SPEAR320-2

Description	Embedded MPU with ARM926 core, optimized for factory automation and consumer applications

PDF	73 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

Logo

56 / 73 page

Timing requirements

SPEAr320

56/73

Doc ID 16755 Rev 5

Figure 12.

Output address signal waveforms for NAND Flash

Figure 13.

In/out data address signal waveforms for NAND Flash

Note:

Values in Table 36 are referred to the common internal source clock which has a period of

tHCLK = 6 ns.

Table 36.

Timing characteristics for NAND Flash

Parameter

Min

Max

tCLE

-3.9

2.8

tALE

-4.2

2.6

tWE (programmable by the Tset

bits in the FSMC registers)

(((Tset+1) * tHCLK ) - 3 ns)

(((Tset+1) * tHCLK) + 3 ns)

tRE (programmable by the Tset

bits in the FSMC registers)

(((Tset+1) * tHCLK ) - 3 ns)

(((Tset+1) * tHCLK) + 3 ns)

tIO (programmable by the Thiz

bits in the FSMC registers)

(((Thiz +1) * tHCLK) - 3 ns)

(((Thiz +1) * tHCLK )+ 3 ns)

tREAD (programmable by the

Twait bits in the FSMC registers)

((Twait+1)* tHCLK

FSMC_ADDR_LE

FSMC_CSx

FSMC_WE

FSMC_Dx

Address

tALE

tWE

tIO

FSMC_CSx

FSMC_WE

FSMC_Dx (out)

Data Out

tIO

FSMC_Dx (in)

FSMC_RE

tRE -> IO

tWE

tRE

tREAD

tNFIO -> FFs

SPEAR320-2 Fiches technique(PDF) 56 Page - STMicroelectronics

SPEAR320-2 Fiches technique(HTML) 56 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Fiches technique Télécharger

Lien URL