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SPEAR320-2 Fiches technique(PDF) 11 Page - STMicroelectronics

No de pièce SPEAR320-2
Description  Embedded MPU with ARM926 core, optimized for factory automation and consumer applications
PDF  73 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR320-2 Fiches technique(HTML) 11 Page - STMicroelectronics

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SPEAr320
Architecture overview
Doc ID 16755 Rev 5
11/73
3
Architecture overview
The SPEAr320 internal architecture is based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix.
The switch matrix structure allows different subsystem dataflow to be executed in parallel
improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller
reducing the memory access latency. The overall memory bandwidth assigned to each
master port can be programmed and optimized through an internal efficient weighted round-
robin arbitration mechanism.
Figure 2.
Typical system architecture using SPEAr320
3.1
CPU ARM 926EJ-S
The core of the SPEAr320 is an ARM926EJ-S reduced instruction set computer (RISC)
processor.
It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off
between high performance and high code density and includes features for efficient
execution of Java byte codes.
Clock, Reset
32 kHz
24 MHz
RTC
8-channel DMA
6 timers / WD
SPEAr320
ARM 926EJ-S
up to 333 MHz
8 KB embed. SRAM
32 KB embed. ROM
MMU
Interrupt/syst controller
GPIO
DDR
memory
controller
DDR2
Mobile DDR
EMI
NOR Flash
NAND Flash
FPGA
EEPROM
SMI
Flash
Debug, trace
JTAG
ETM9
2x I2C
Internet
Access
Phy
IrdDA
USB2.0 PHY
device
USB2.0 PHY
Host
USB2.0 PHY
Host
3x UART
JPEG CODEC
accelerator
C3 Crypto
accelerator
2x Ethernet
FSMC
3x SSP
CAN
SDIO/MMC
MMC
SD-Card
SDIO
ADC
TouchScreen
LCD
controller
4x PWM
Parallel
port
2x CAN
Controller Area Network



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