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CY2303 Fiches technique(PDF) 5 Page - Cypress Semiconductor

No de pièce CY2303
Description  Phase-Aligned Clock Multiplier
PDF  14 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2303 Fiches technique(HTML) 5 Page - Cypress Semiconductor

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CY2303
Document Number: 38-07249 Rev. *F
Page 5 of 14
Switching Characteristics
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
1/t1
Output frequency
18-pF load
10
133.33
MHz
12-pF load
166.67
MHz
Duty cycle [3] = t2 t1
Measured at VDD/2
40
50
60
%
t3
Rise time [3]
Measured between 0.8 V and 2.0 V
1.20
ns
t4
Fall time [3]
Measured between 0.8 V and 2.0 V
1.20
ns
t5
Output to output skew on rising
edges [3]
All outputs equally loaded
Measured at VDD/2
200
ps
t6
Delay, REFIN rising edge to REF
rising edge [3]
Measured at VDD/2 from REFIN to
any output
200
ps
t7
Device to device skew [3]
Measured at VDD/2 on the REF pin
of the device (pin 1)
400
ps
tJ
Period jitter [3]
Measured at FOUT < 133.33 MHz,
loaded outputs, 18-pF load
80
175
ps
tLOCK
PLL lock time [3]
Stable power supply, valid clocks
presented on REFIN
1.0
ms
Note
3. All parameters are specified with loaded outputs.



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