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A32100DX Fiches technique(PDF) 49 Page - Actel Corporation

No de pièce A32100DX
Description  HiRel FPGAs
PDF  98 Pages
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Fabricant  ACTEL [Actel Corporation]
Site Internet  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX Fiches technique(HTML) 49 Page - Actel Corporation

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49
Hi R e l F P GA s
A3 21 00 DX Ti m i n g Ch ar ac te r i st i c s (continued)
(Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
’–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
8.8
11.8
ns
tWC
Write Cycle Time
8.8
11.8
ns
tRCKHL
Clock High/Low Time
4.4
5.9
ns
tRCO
Data Valid After Clock High/Low
4.4
5.9
ns
tADSU
Address/Data Setup Time
2.1
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
ns
tRENSU
Read Enable Setup
0.8
1.1
ns
tRENH
Read Enable Hold
4.4
5.9
ns
tWENSU
Write Enable Setup
3.5
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
ns
tBENS
Block Enable Setup
3.6
4.8
ns
tBENH
Block Enable Hold
0.0
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
10.6
14.1
ns
tRDADV
Read Address Valid
11.5
15.3
ns
tADSU
Address/Data Setup Time
2.1
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
ns
tRENSUA
Read Enable Setup to Address Valid
0.8
1.1
ns
tRENHA
Read Enable Hold
4.4
5.9
ns
tWENSU
Write Enable Setup
3.5
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
ns
tDOH
Data Out Hold Time
1.6
2.1
ns



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