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CXD3003R Fiches technique(PDF) 7 Page - Sony Corporation

No de pièce CXD3003R
Description  CD Digital Signal Processor with Built-in Digital Servo and DAC
PDF  137 Pages
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Fabricant  SONY [Sony Corporation]
Site Internet  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD3003R Fiches technique(HTML) 7 Page - Sony Corporation

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CXD3003R
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O
O
I
O
O
O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
O
O
O
O
I/O
I
O
O
O
1, Z, 0
1, 0
1, Z, 0
1, Z, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
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1, 0
1, Z, 0
1, Z, 0
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1, 0
Channel 2 DAC PWM output (forward phase).
Analog power supply.
Master clock power supply.
Master clock crystal oscillation circuit output.
Master clock crystal oscillation circuit input.
Master clock GND.
Analog GND.
Channel 1 DAC PWM output (forward phase).
Channel 1 DAC PWM output (reversed phase).
Analog power supply.
Digital power supply.
SENS output to CPU.
Used during 1-track jumps.
SENS serial data readout clock input.
Anti-shock pin.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Digital GND.
Track count signal I/O.
Mirror signal I/O.
Defect signal I/O.
Focus OK signal I/O.
Test pin. Leave this open.
Spindle motor external pin input.
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
Spindle motor on/off control output.
Spindle motor servo control output.
Spindle motor servo control output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high.
Disc innermost track detection signal input.
Digital GND.
Sled drive output.
Sled drive output.
Tracking drive output.
AO2F
AVDD4
AVDD5
XTLO
XTLI
AVSS5
AVSS3
AO1F
AO1R
AVDD3
AVDD4
SENS
DIRC
SCLK
ATSK
DATA
XLAT
CLOK
DVSS4
COUT
MIRR
DFCT
FOK
TESTA
PWMI
FSW
MON
MDP
MDS
LOCK
SSTP
DVSS5
SFDR
SRDR
TFDR
Pin
No.
Symbol
I/O
Description



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